#ifndef _ASMARM_CACHEFLUSH_H
#define _ASMARM_CACHEFLUSH_H

// #define __cpuc_flush_kern_all		cpu_cache.flush_kern_all
#define __cpuc_flush_kern_all		v7_flush_kern_cache_all

// #define __cpuc_coherent_kern_range	cpu_cache.coherent_kern_range
#define __cpuc_coherent_kern_range	v7_coherent_kern_range

// #define __cpuc_flush_dcache_page	cpu_cache.flush_kern_dcache_page
#define __cpuc_flush_dcache_page	v7_flush_kern_dcache_page

// #define cpu_dcache_clean_area		__cpu_fn(CPU_NAME,_dcache_clean_area)
#define cpu_dcache_clean_area		cpu_v7_dcache_clean_area

#define flush_icache_range(s,e)		__cpuc_coherent_kern_range(s,e)

#define flush_cache_all()		__cpuc_flush_kern_all()

/*
 * Perform necessary cache operations to ensure that the TLB will
 * see data written in the specified area.
 */
#define clean_dcache_area(start,size)	cpu_dcache_clean_area(start, size)

static inline void __flush_icache_all(void)
{
// #ifdef CONFIG_ARM_ERRATA_411920
// 	extern void v6_icache_inval_all(void);
// 	v6_icache_inval_all();
// #else
	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
	    :
	    : "r" (0));
// #endif
}

#endif
